This invention relates to a driver circuit for a device such as a liquid crystal display (LCD), more particularly to a driver circuit suited for high-speed cascaded operation.
Driver circuits for large LCDs must provide parallel output on numerous signal lines, such as 640 signal lines or more. This far exceeds the output pin count of even a large integrated circuit (IC), so it is common for several driver ICs to be interconneted in cascade. For example, eight ICs with 80 output pins each, or four ICs of the tape-automated bonding (TAB) type with 160 output pins each, can be cascaded to drive 640 signal lines.
In such a cascaded configuration the input data are provided in serial form to all the driver ICs in common. Each IC also receives an enable signal from the preceding IC in the cascade. The ICs latch the serial input data in turn: the first-stage IC latches the first N bits, the second-stage IC latches the next N bits, and so on. As soon as it finishes latching its own N bits of data, each IC must promptly assert its enable signal so that the next-stage IC can begin latching the next N bits.
To assert the enable signal, an IC must generate the enable signal internally and output it on an external signal line. The enable signal must then be received, amplified and stored in a latch in the next-stage IC. These processes take a certain amount of time, due to internal gate and amplifier propagation delays, the propagation delay on the external signal line, and the need to satisfy latch setup requirements.
A problem is that these processes must be completed within one clock cycle: for example, the clock cycle during which the first-stage IC latches the N-th bit. Consequently, the following condition must be satisfied: EQU clock cycle time.gtoreq.enable delay time+enable setup time
If the ICs are fabricated by CMOS technology with 4-micron design rules, the enable delay time is substantially 170 ns while the setup time is substantially 40 ns, so the clock cycle can be no shorter than substantially 210 ns and the clock rate no faster than substantially 4.76 MHz.
This speed is unsatisfactory: in many applications it would be desirable to transfer 64,000-bit data 80 times per second, requiring a 5.12-MHz clock, and future high-resolution LCDs will require even faster clock rates. The delay and setup requirements of the enable signal in a cascade configuration are the chief obstacle to the attainment of such rates.